1 CAT24WC164 16k-bit serial eeprom, cascadable * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. pin configuration block diagram pin functions pin name function a0, a1, a2 device address inputs sda serial data/address scl serial clock wp write protect v cc +1.8v to +6.0v power supply v ss ground dip package (p, l) soic package (j, w) 5020 fhd f01 features 400 khz i 2 c bus compatible* 1.8 to 6.0 volt operation low power cmos technology write protect feature - entire array protected when wp at v ih page write buffer self-timed write cycle with auto-clear 1,000,000 program/erase cycles 100 year data retention 8-pin dip, 8-pin soic, 8-pin msop or 8 pin tssop (also available in "green" packages) industrial, automotive and extended temperature ranges description the CAT24WC164 is a16k-bit, cascadable serial cmos eeprom internally organized as 2048 words of 8 bits each. catalysts advanced cmos technology substan- tially reduces device power requirements. the CAT24WC164 features a 16-byte page write buffer. the device operates via the i 2 c bus serial interface, has a special write protection feature, and is available in 8-pin dip, 8-pin soic, 8-pin tssop and 8-lead msop. ? 2004 by catalyst semiconductor, inc. characteristics subject to change without notice tssop package (u, y) doc. no. 1026, rev. h msop package (r, z) v cc scl sda 1 2 3 4 8 7 6 5 v ss a2 a0 a1 wp h a l o g e n f r e e tm l e a d f r e e a 2 a 0 a 1 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda a 0 v cc wp scl sda 1 2 3 4 8 7 6 5 a 1 a 2 v ss d out ack sense amps shift registers control logic word address buffers start/stop logic state counters slave address comparators e 2 prom v cc external load column decoders xdec data in storage high voltage/ timing control v ss wp scl a 0 a1 a2 sda 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 v ss 1 2 3 4
CAT24WC164 2 doc. no. 1026, rev. h reliability characteristics symbol parameter reference test method min typ max units n end (3) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (3) data retention mil-std-883, test method 1008 100 years v zap (3) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (3)(4) latch-up jedec standard 17 100 ma capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol parameter test conditions min typ max units c i/o (3) input/output capacitance (sda) v i/o = 0v 8 pf c in (3) input capacitance v in = 0v 6 pf (a0, a1, a2, scl, wp) d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. symbol parameter test conditions min typ max units i cc power supply current f scl = 100 khz 3 ma i sb (5) standby current (v cc = 5.0v) v in = gnd or v cc 1 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage C 1v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage (v cc = 3.0v) i ol = 3 ma 0.4 v v ol2 output low voltage (v cc = 1.8v) i ol = 1.5 ma 0.5 v absolute maximum ratings* temperature under bias ................. C 55 c to +125 c storage temperature ....................... C 65 c to +150 c voltage on any pin with respect to ground (1) ........... C 2.0v to +v cc + 2.0v v cc with respect to ground ............... C 2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. note: (1) the minimum dc input voltage is C 0.5v. during transitions, inputs may undershoot to C 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1v to v cc +1v. (5) maximum standby current (i sb ) = 10 a for the automotive and extended automotive temperature range.
CAT24WC164 3 doc. no. 1026, rev. h write cycle limits symbol parameter min typ max units t wr write cycle time 5 ms a.c. characteristics v cc = +1.8v to +6.0v, unless otherwise specified. read & write cycle limits symbol parameter 1.8 v - 6.0 v 2.5 v - 6.0 v min max min max units f scl clock frequency 100 400 khz t i (1) noise suppression time 200 200 ns constant at scl, sda inputs t aa scl low to sda data out 3.5 1 s and ack out t buf (1) time the bus must be free before 4.7 1.2 s a new transmission can start t hd:sta start condition hold time 4 0.6 s t low clock low period 4.7 1.2 s t high clock high period 4 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 50 50 ns t r (1) sda and scl rise time 1 0.3 s t f (1) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t dh data out hold time 100 100 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. power-up timing (1)(2) symbol parameter min typ max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms
CAT24WC164 4 doc. no. 1026, rev. h functional description the CAT24WC164 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. data transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the CAT24WC164 operates as a slave device. both the master and slave devices can operate as either transmitter or receiver, but the master device controls which mode is activated. a maximum of 8 devices may be connected to the bus as determined by the device address inputs a0, a1, and a2. pin descriptions scl: serial clock the CAT24WC164 serial clock input pin is used to clock all data transfers into or out of the device. this is an input pin. sda: serial data/address the CAT24WC164 bidirectional serial data/address pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. a0, a1, a2: device address inputs these inputs set device address when cascading multiple devices. when these pins are left floating the default values are zeros. a maximum of eight devices can be cascaded. if only one CAT24WC164 is addressed on the bus, all three figure 2. write cycle timing figure 1. bus timing figure 3. start/stop timing t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh t wr stop condition start condition address ack 8th bit byte n scl sda start bit sda stop bit scl
CAT24WC164 5 doc. no. 1026, rev. h address pins (a0, a1and a2) can be left floating or connected to v ss . the CAT24WC164 can be made compatible with the cat24wc16 by tying a2, a1 and a0 to vss or by leaving a2, a1 and a0 float. wp: write protect if the wp pin is tied to v cc the entire memory array becomes write protected (read only). when the wp pin is tied to v ss or left floating normal read/write operations are allowed to the device. i 2 c bus protocol the following defines the features of the i 2 c bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the CAT24WC164 monitor the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the most significant bit of the 8-bit slave address is fixed as 1. (see fig. 5). the next three significant bits (a2, a1, a0) are the device address bits and define which device or which part of the device the master is accessing (the a1 bit must be the compliment of the a1 input pin signal). up to eight CAT24WC164 devices may be individually addressed by the system. the next three bits are used as the three most significant bits of the data word address. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the CAT24WC164 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the CAT24WC164 then performs a read or write operation depending on the state of the r/ w bit. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowl- edging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the CAT24WC164 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. figure 4. acknowledge timing acknowledge 1 start scl from master 89 data output from transmitter data output from receiver
CAT24WC164 6 doc. no. 1026, rev. h when the CAT24WC164 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the CAT24WC164 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends the remainder of the byte address that is to be written into the address pointer of the CAT24WC164. after receiving another acknowledge from the slave, the master device transmits the data byte to be written into the addressed memory location. the CAT24WC164 acknowledge once more and the master generates the stop condition, at which time the device begins its internal programming cycle to nonvolatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the CAT24WC164 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial word is transmitted, the master is allowed to send up to fifteen additional bytes. after each byte has been transmitted the CAT24WC164 will respond with an acknowledge, and internally increment the low order address bits by one. the high order bits remain unchanged. if the master transmits more than sixteen bytes prior to sending the stop condition, the address counter wraps around , and previously transmitted data will be overwritten. once all sixteen bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point all received data is written to the CAT24WC164 in a single write cycle. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host s write operation, the CAT24WC164 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the CAT24WC164 is still busy with the write operation, no ack will be returned. if the CAT24WC164 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection the write protection feature allows the user to protect against inadvertent programming of the memory array. if the wp pin is tied to v cc , the entire memory array is protected and becomes read only. the CAT24WC164 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device s failure to send an acknowledge after the first byte of data is received. figure 5. slave address bits ** a8, a9 and a10 correspond to the address of the memory array address word. *** a0, a1 and a2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3). 1 a2 a1 a0 a10 a9 a8 r/w CAT24WC164
CAT24WC164 7 doc. no. 1026, rev. h figure 7. page write timing figure 6. byte write timing read operations the read operation for the CAT24WC164 is initiated in the same manner as the write operation with the one exception that the r/ w bit is set to a one. three different read operations are possible: immediate address read, selective read and sequential read. immediate address read the device address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n+1. if n=2047, then the counter will 'wrap around' to addrss 0 and continue to clock out data. after the CAT24WC164 receives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the CAT24WC164 acknowledge the word address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the CAT24WC164 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the CAT24WC164 sends initial 8-bit byte requested, the master will respond with an acknowledge which tells the device it requires more data. the CAT24WC164 will continue to output an 8-bit byte for each acknowledge sent by the master. the operation is terminated when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from the CAT24WC164 is outputted sequentially with data from address n followed by data from address n+1. the read operation address counter increments all of the CAT24WC164 address bits so that the entire memory array can be read during one operation. if more than the 2047 bytes are read out, the counter will wrap around and continue to clock out data bytes. byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t bus activity: master sda line data n+15 byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address note: in this example n = xxxx 0000(b); x = 1 or 0
CAT24WC164 8 doc. no. 1026, rev. h figure 10. sequential read timing figure 9. selective read timing figure 8. immediate address read timing bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t scl sda 8th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t
CAT24WC164 9 doc. no. 1026, rev. h notes: (1) the device used in the above example is a CAT24WC164ji-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating voltage, tape & reel). (2) product die revision letter is marked on top of the package as a suffix to the production date code (e.g. aywwf). for addit ional informa- tion, please contact your catalyst sales office. ordering information prefix device # suffix 24wc164 j i te13 product number 24wc164: 16k tape & reel te13: 2000/reel package p: pdip j: soic (jedec) u: tssop operating voltage blank: 2.5v - 6.0v 1.8: 1.8v - 6.0v -1.8 cat temperature range i = industrial (-40 to 85 c) a = automotive (-40 to 105 c)* optional company id r: msop l: pdip (lead free, halogen free) w: soic (lead free, halogen free) y: tssop (lead free, halogen free) z: msop (lead free, halogen free) e = extended (-40 to 125 c) rev f (2) die revision
CAT24WC164 10 doc. no. 1026, rev. h catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1026 revison: h issue date: 8/3/04 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date rev. reason 12/29/2003 f added 8-pin msop package to features section deleted 2.5v - 6.0v from ac characteristics changed 4.5v - 5.5v to 2.5v - 6.0v in ac characteristics changed max to 5 in write cycle limits (t wr ) added overbar to a1 in figure 5 (slave address bits) 7/23/2004 g added die revision to ordering information 8/3/2004 h update dc operating characteristics table & notes
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